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| ST16C452 ST16C452PS DUAL UART WITH PARALLEL PRINTER PORT March 2004 DESCRIPTION The ST16C452/ST16C452PS (452/452PS) is a dual universal asynchronous receiver and transmitter (UART) with an added bi-directional parallel port that is directly compatible with a CENTRONICS type printer. The parallel port is designed such that the user can configure it as general purpose I/O interface, or for connection to other printer devices. The 452/452PS provides enhanced UART functions, a modem control interface, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status. The system interrupts and control may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. A programmable baud rate generator is provided to select transmit and receive clock rates from 50 bps to 1.5 Mbps. The 452/452PS is available in a 68 pin PLCC package. The 452/452PS is compatible with the 16C450. The 452 is available in two versions, the ST16C452 and the ST16C452PS. The ST16C452 provides single hardware pin to control the printer port data direction while the 452PS provides an additionally software control bit to control the printer port data direction to become compatible PS/2 operating system. The 452/452PS is fabricated in an advanced CMOS process with low power consumption. PLCC Package FEATURES ERROR -DSRB -BUSY BIDEN SLCT -CDB -CSB GND GND VCC ACK RXB 62 N.C. Added features in devices with top mark date code of "F2 YYWW" and newer: * 5V Tolerant Inputs * Pin to pin and functional compatible to TL16C452 * 2.97 to 5.5 volt operation * Software compatible with ST16C450, NS16C450 * 1.5 Mbps transmit/receive operation (24MHz) * Independent transmit and receive control * Modem and printer status registers * UART port and printer port Bi-directional * Printer port direction set by single control bit or 8 bit pattern (AA/55) * Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD) * Programmable character lengths (5, 6, 7, 8) * Even, odd, or no parity bit generation and detection * Internal loop-back diagnostics * TTL compatible inputs, outputs * Low Power 68 67 66 65 64 63 61 60 59 58 57 56 55 54 9 8 7 6 5 4 3 2 TXB -DTRB -RTSB -CTSB D0 D1 D2 D3 D4 D5 D6 D7 N.C. VCC -RTSA -DTRA TXA 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 1 N.C. -RIB CLK PE INTB INTP -SLCTIN INIT -AUTOFDXT -STROBE GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 INTA RDOUT ST16C452CJ68 ST16C452CJ68PS 53 52 51 50 49 48 47 46 45 44 A2 A1 A0 -RESET ORDERING INFORMATION Part number Package Operating temperature Device Status ST16C452CJ68 ST16C452CJ68PS ST16C452IJ68 ST16C452IJ68PS 68-Lead 68-Lead 68-Lead 68-Lead PLCC PLCC PLCC PLCC 0 C to + 70 C 0 C to + 70 C -40 C to + 85 C -40 C to + 85 C Active Active Active Active Rev. 3.20 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 INTSEL -CDA -CSA -CSP GND -IOW -DSRA -CTSA -IOR VCC RXA -RIA N.C. ST16C452/452PS Figure 1, Block Diagram Data bus & Control Logic D0-D7 -IOR -IOW -RESET BIDEN Transmit Holding Registers Receive Holding Registers Transmit Shift Register Receive Shift Register Printer Data Ports TX A,B RX A,B Inter Connect Bus Lines & Control signals PD0-PD7 -STROBE INIT -AUTOFDX -SELCTIN PE, SELECT -BUSY, -ACK ERROR -DTR A,B -RTS A,B A0-A2 -CSA -CSB -CSP Register Select Logic Printer Control Logic INT A,B INTP Clock & Baud Rate Generator Interrupt Control Logic Modem Control Logic -CTS A,B -RI A,B -CD A,B -DSR A,B Rev. 3.20 2 CLK ST16C452/452PS SYMBOL DESCRIPTION Symbol Pin Signal Type Pin Description A0 A1 A2 -ACK 35 34 33 68 I I I I Address-0 Select Bit - Internal registers address selection. Address-1 Select Bit - Internal registers address selection. Address-2 Select Bit - Internal registers address selection. Acknowledge (with internal pull-up) - General purpose input or line printer acknowledge (active low). a logic 0 from the printer, indicates successful data transfer to the print buffer. General purpose I/O (open drain, with internal pull-up) or automatic line feed (open drain input with internal pull-up). When this signal is low the printer should automatically line feed after each line is printed. Bi-Direction Enable - PD7-PD0 direction select. A logic 0 sets the parallel port for I/O Select Register Control. A logic 1 sets the parallel port for Control Register Bit-5 Control. Busy (with internal pull-up) - General purpose input or line printer busy (active high). can be used as an output from the printer to indicate printer is not ready to accept data. Clock Input. - An external clock must be connected to this pin to clock the baud rate generator and internal circuitry (see Programmable Baud Rate Generator). Chip Select A - A logic 0 at this pin enables the serial channel-A UART registers for CPU data transfers. Chip Select B - A logic 0 at this pin enables the serial channel-B UART registers for CPU data transfers. Printer Port Chip Select - (active low). A logic 0 at this pin enables the parallel printer port registers and/or PD7-PD0 for external CPU data transfers. Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. -AutoFDXT 56 I/O BIDEN 1 I BUSY 66 I CLK 4 I -CSA 32 I -CSB 3 I -CSP 38 I D0-D7 14-21 I/O Rev. 3.20 3 ST16C452/452PS SYMBOL DESCRIPTION Symbol Pin Signal Type Pin Description -ERROR 63 I Error, Printer (with internal pull-up) - General purpose input or line printer error. This pin may be connected to the active low (logic 0) output of a printer to indicate an error condition. Signal and Power Ground. GND 2,7,54 27 57 Pwr INIT I/O Initialize (open drain, with internal pull-up) - General purpose I/O signal. This pin may be connected for initialization service of a connected line printer. Generally when this signal is a logic 0, any connected printer will be initialized. Interrupt output A/B ( three state active high) - These pins provide individual channel interrupts, INT A-B. INT A-B are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. Printer Interrupt, - This pin can be used to signal the interrupt status of a connected printer. This pin basically tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts are enabled by bit-4 in the control register. A latched mode can be selected by setting INTSEL to a logic 1. In this case the interrupt -INTP is generated normally but does not return to the inactive state until the trailing edge of the read cycle (-IOR pin). -INTP is three stated until CON bit-4 is set to a logic 1. Interrupt Select mode - This pin selects the interrupt type for the printer port (-INTP). When this pin is a logic 0, the external -ACK signal state is generally followed, minus some minor propagation delay. Making this pin a logic 1 or connecting it to VCC will set the interrupt latched mode. In this case the printer interrupt (-INTP) will not return to a logic 1 until the trailing edge of -IOR (end of the external CPU read cycle). Read strobe.- A logic 0 transition on this pin will place the contents of an Internal register defined by address bits A0-A2 INT A/B 45,60 O -INTP 59 O INTSEL 43 I -IOR 37 I Rev. 3.20 4 ST16C452/452PS SYMBOL DESCRIPTION Symbol Pin Signal Type Pin Description for either UART channels A/B or A0-A1 for the printer port, onto D0-D7 data bus for a read cycle by an external CPU. -IOW 36 I Write strobe.- A logic 0 transition on this pin will transfer the data on the internal data bus (D0-D7), as defined by either address bits A0-A2 for UART channels A/B or A0-A1 for the printer port, into an internal register during a write cycle from an external CPU. Printer Data port (Bi-directional three state) - These pins are the eight bit, three state data bus for transferring information to or from an external device (usually a printer). D0 is the least significant bit. PD7-PD0 are latched during a write cycle (output mode). Paper Empty - General purpose input or line printer paper empty (Internal pull-up). This pin can be connected to provide a printer out of paper indication. Read Out (active high) - This pin goes to a logic 1 when the external CPU is reading data from the 452/452PS. This signal can be used to enable/disable external transceivers or other logic functions. Master Reset (active low) - a logic 0 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C452/452PS External Reset Conditions for initialization details.) Not Used. Should be left open. PD7-PD0 46-53 I/O PE 67 I RDOUT 44 O -RESET 39 I N.C. SLCT 9,61 65 I Select (with internal pull-up) - General purpose input or line printer select status. Normally this pin is connected to a printer output (active low) that indicates the ready status of a printer, i.e., on-line and/or on-line and ready. Select In (open drain, with internal pull-up) - General purpose I/O or line printer select. This pin can be read via Bit-3 in the printer command register, or written via bit-3 in the printer control register. As this pin is open-drain, it can be wire-or'd with other outputs. Normally this signal is connected -SLCTIN 58 I/O Rev. 3.20 5 ST16C452/452PS SYMBOL DESCRIPTION Symbol Pin Signal Type Pin Description with a printer to select the printer with an active low. -STROBE 55 I/O Strobe (open drain, with internal pull-up) - General purpose I/O or data strobe output. Normally this output is connected to a printer and indicates that valid data is available at the printer port (PD0-PD7). Not Used. Should be left open. N.C. VCC 22,42 23,40,64 Pwr 2.97 to 5.5V power supply input. All inputs are 5V tolerant except for XTAL1 and all printer port inputs for devices with top mark date code of "F2 YYWW" and newer. Carrier Detect (active low) - These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. Clear to Send (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin(s) indicates the modem or data set is ready to accept transmit data from the 452/452PS for the given channel. Status can be tested by reading MSR bit-4 for that channel(s). -CTS has no effect on the transmit or receive operation. Data Set Ready (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin(s) indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART's transmit or receive operation. Data Terminal Ready (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on this pin(s) indicates that the 452/452PS is powered-on and ready. This pin can be controlled via the modem control register for channel(s) A-B. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This pin has no effect on the UART's transmit or receive operation. Ring Indicator (active low) - These inputs are associated with -CD A/B 29,8 I -CTS A/B 28,13 I -DSR A/B 31,5 I -DTR A/B 25,11 O -RI A/B 30,6 I Rev. 3.20 6 ST16C452/452PS SYMBOL DESCRIPTION Symbol Pin Signal Type Pin Description individual UART channels, A through B. A logic 0 on this pin(s) indicates the modem has received a ringing signal from the telephone line(s). A logic 1 transition on this input pin will generate an interrupt for the ringing channel(s). This pin does not have any effect on the transmit or receive operation. -RTS A/B 24,12 O Request to Send (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on the -RTS pin(s) indicates the transmitter has data ready and waiting to send for the given channel(s). Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin does not have any effect on the transmit or receive operation. Receive Data Input, RX A-B. - These inputs are associated with individual serial channel(s) to the 452. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pins are disabled and TX data is internally connected to the UART RX Inputs, internally. Transmit Data, TX A-B - These outputs are associated with individual serial transmit channel(s) from the 452/452PS. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX output pins are disabled and TX data is internally connected to the UART RX Inputs. RX A/B 41,62 I TX A/B 26,10 O Rev. 3.20 7 ST16C452/452PS GENERAL DESCRIPTION The 452/452PS provides serial asynchronous receive data synchronization, parallel-to-serial and serial-toparallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 452/452PS represents such an integration with greatly enhanced features. The 452/452PS is fabricated with an advanced CMOS process. The 452/452PS combines the package functions of a dual UART and a printer interface on a single integrated chip. The 452/452PS UART is indented to be software compatible with the ST16C450, and NS16C450 while the bi-directional printer interface mode is intended to operate with a CENTRONICS type parallel printer. However, the printer interface is designed such that it may be configured to operate with other parallel printer interfaces or used as a general purpose parallel interface. The 452 is available in two versions, the ST16C452 and the ST16C452PS. The ST16C452 provides single hardware pin to control the printer port data direction while the 452PS provides an additionally software control bit to control the printer port data direction to become compatible PS/2 operating system. The 452/452PS is capable of operation to 1.5Mbps with a 24 MHz external clock input. With an external clock input of 1.8432 MHz the user can select data rates up to 115.2 Kbps. FUNCTIONAL DESCRIPTIONS Functional Modes Two functional user modes are selectable for the 452/ 452PS package. The first of these provides the dual UART functions, while the other provides the functions of a parallel printer interface. These features are available through selection at the package interface select pins. UART A-B Functions The UART mode provides the user with the capability to transfer information between an external CPU and the 452/452PS package. A logic 0 on chip select pins -CSA or -CSB allows the user to configure, send data, and/or receive data via the UART channels A-B. Printer Port Functions The Printer mode provides the user with the capability to transfer information between an external CPU and the 452/452PS parallel printer port. A logic 0 on chip select pin -CSP allows the user to configure, send data, and/or receive data via the bi-directional parallel 8-bit data bus, PD0-PD7. Internal Registers The 452/452PS provides 11 internal registers for monitoring and control of the UART functions and another 6 registers for monitoring and controlling the printer port. These resisters are shown in Table 4 below. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). The printer port registers functions data holding registers (PR), I/O status register (SR), I/O select register (IOSEL), and a command and control register (COM/CON). Register functions are more fully described in the following paragraphs. Rev. 3.20 8 ST16C452/452PS Table 4, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1* 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3 X X X 0 0 1 0 1 0 PORT REGISTER STATUS REGISTER COMMAND REGISTER PORT REGISTER I/O SELECT REGISTER CONTROL REGISTER Note 1* The General Register set is accessible only when CS A or CS B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1. Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the interface signal BIDEN and Printer Control Register bit-5 or IOSEL register. Programmable Baud Rate Generator The 452/452PS supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 452/452PS can support a standard data rate of 921.6Kbps. Single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 452/452PS requires that an external clock source be connected to the CLK input pin to clock the internal baud rate generator for standard or custom rates. (see Baud Rate Generator Programming below). Rev. 3.20 9 ST16C452/452PS The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 452/452PS divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 5 below, shows the selectable baud rate table available when using a 1.8432 MHz external clock input. Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK): Output Baud Rate Output 16 x Clock Divisor (Decimal) 2304 1047 768 384 192 96 48 24 16 12 6 3 2 1 User 16 x Clock Divisor (HEX) 900 417 300 180 C0 60 30 18 10 0C 06 03 02 01 DLM Program Value (HEX) 09 04 03 01 00 00 00 00 00 00 00 00 00 00 DLL Program Value (HEX) 00 17 00 80 C0 60 30 18 10 0C 06 03 02 01 50 110 150 300 600 1200 2400 4800 7200 9600 19.2k 38.4k 57.6k 115.2k Loop-back Mode The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR register bits 0-3 are used for controlling loop-back diagnostic testing. In the loop-back mode INT enable and MCR bit-2 in the MCR register (bits 2,3) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 6). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, INT enable and MCR bit-2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then made Rev. 3.20 10 ST16C452/452PS available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. Figure 6, INTERNAL LOOP-BACK MODE DIAGRAM Receive Holding Registers Receive Shift Register MCR Bit-4=1 RX A,B PD0-PD7 -STROBE INIT -AUTOFDX -SELCTIN PE, SELECT -BUSY, -ACK ERROR -RTS -CD -DTR -RI (-OP1) -DSR (-OP2) -CTS D0-D7 -IOR -IOW -RESET BIDEN Data bus & Control Logic Transmit Holding Registers Transmit Shift Register TX A,B Printer Data Ports Inter Connect Bus Lines & Control signals A0-A2 -CSA -CSB -CSP Register Select Logic Printer Control Logic INT A,B INTP Clock & Baud Rate Generator Interrupt Control Logic Rev. 3.20 11 CLK Modem Control Logic ST16C452/452PS Printer Port The 452/452PS contains a general purpose 8-bit parallel interface port that is designed to directly interface with a CENTRONICS Printer. A number of the control/interrupt signals and the 8-bit data bus have been designed as bi-directional data buses. This allows the interface to function with other device parallel data bus applications. Signal -ACK is used to generate an -INTP interface interrupt that would normally be connected to the user CPU. -INTP can be made to follow the -ACK signal, normal mode (see Figure 7) or it can be configured for the latch mode. In the latch mode the interrupt is not cleared until printer status register (SR) is read. Another signal (INIT) can be made to function as an outgoing or incoming interrupt, or combined with other interrupts to provide a common wire-or interrupt output. Interface signals STROBE, -AutoFDXT, and -SLCTIN are bi-directional and can be used as combinations of input and/ or output functions. The signals have internal pull-up resistors and can be wire-or'd. Normally, -STROBE is used to strobe PD0-PD7 bus data into a printer input buffer. -SLCTIN normally selects the printer while AutoFDXT signals the printer to auto-linefeed. Other signals provide similar printer functions but are not bidirectional. The printer functions for these signals are described in table 1, Symbol Description. The interface provides a mode steering signal called BIDEN. BIDEN controls the bi-directional 8-bit data bus (PD0-PD7) direction, input or output. This pin controls the port direction in the ST16C452. A logic 0 on this pin places the parallel port in the output mode and a logic 1 places the parallel port in the input mode. In the ST16C452PS, the port direction is determined as described in Table 6. When BIDEN is a logic 1 a single control bit (D5) in the control register sets the input or output mode. Setting BIDEN to a logic 0 however sets an IBM interface compatible mode. In this mode the bus direction (input/output) is set by eight data bits in the IOSEL register. An AA (Hex) pattern sets the input mode while a 55 (hex) pattern sets the output mode. I/ O direction is depicted in Table 6 below. Table 6, PD0-PD7 I/O DIRECTION MODE SELECTION [452PS only] PORT DIRECTION Input mode Output mode Output mode Input mode Note: 4 = don't care BIDEN 0 0 1 1 CONTROL REGISTER (D5) X (Note 4) X (Note 4) 0 1 I/O SELECT REGISTER AA Hex 55 Hex X (Note 4) X (Note 4) Rev. 3.20 12 ST16C452/452PS REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the eighteen 452/452PS internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 7, ST16C452/452PS INTERNAL REGISTERS A2 A1 A0 Register [Default] Note 5* BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 General Register Set: Note 1* 0 0 0 0 0 0 0 0 1 RHR [XX] THR [XX] IER [00] bit-7 bit-7 0 bit-6 bit-6 0 bit-5 bit-5 0 bit-4 bit-4 0 bit-3 bit-3 Modem Status Interrupt bit-2 bit-2 Receive Line Status interrupt INT priority bit-1 stop bits bit-1 bit-1 Transmit Holding Register interrupt INT priority bit-0 word length bit-1 -RTS bit-0 bit-0 Receive Holding Register 0 1 0 ISR [01] 0 0 0 0 INT priority bit-2 parity enable INT status 0 1 1 LCR [00] divisor latch enable 0 set break set parity even parity word length bit-0 -DTR 1 0 0 MCR [00] 0 0 loop back INT A/B enable [X] 1 0 1 LSR [60] 0 THR & TSR empty RI THR. empty break interrupt framing error parity error overrun error receive data ready delta -CTS bit-0 1 1 0 MSR [X0] CD DSR CTS delta -CD bit-3 delta -RI bit-2 delta -DSR bit-1 1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 Special Register Set: Note *2 0 0 0 0 0 1 DLL [XX] DLM [XX] bit-7 bit-15 bit-6 bit-14 bit-5 bit-13 bit-4 bit-12 bit-3 bit-11 bit-2 bit-10 bit-1 bit-9 bit-0 bit-8 Rev. 3.20 13 ST16C452/452PS A2 A1 A0 Register [Default] Note 5* BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 Printer Port Register Set: Note 3* [X] 0 [X] 0 [X] 0 0 0 1 PR[00] PR[00] SR[4F] bit-7 bit-7 -Busy bit-6 bit-6 -ACK bit-5 bit-5 PE bit-4 bit-4 SLCT bit-3 bit-3 Error State bit-3 -SLCTIN bit-2 bit-2 -IRQ bit-1 bit-1 logic "1" bit-1 -Auto FDXT -Auto FDXT bit-0 bit-0 logic "1" bit-0 -STROBE [X] 0 [X] 1 1 0 IOSEL COM[E0] bit-7 logic "1" [X] bit-6 logic "1" [X] bit-5 logic "1" PD 0-7 IN/OUT bit-4 -INTP Enable -INTP Enable bit-2 INIT [X] 1 0 CON[00] -SLCTIN INIT -STROBE Note 1* The General Register set is accessible only when CS A or CS B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1. Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the interface signal BIDEN and Printer Control Register bit-5 or IOSEL register. Note 5* The value between the square brackets represents the register's initialized HEX value, X = N/A. UART REGISTER DESCRIPTIONS Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = Buffer full). The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 452/452PS by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. Rev. 3.20 14 ST16C452/452PS Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A,B output pins. IER BIT-3: Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt. IER BIT 4-7: Not Used - initialized to a logic 0. Interrupt Status Register (ISR) The 452/452PS provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 8 (below) shows the data values (bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: IER BIT-0: This interrupt will be issued when the RHR is full or is cleared when the RHR is empty. Logic 0 = Disable the receiver ready interrupt. (normal default condition) Logic 1 = Enable the receiver ready interrupt. IER BIT-1: This interrupt will be issued whenever the THR is empty and is associated with bit-1 in the LSR register. Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: This interrupt will be issued whenever a fully assembled receive character is transferred from the RSR to the RHR, i.e., data ready, LSR bit-0. Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt. Table 8, INTERRUPT SOURCE TABLE Priority Level 1 2 3 4 [ISR BITS] Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) Rev. 3.20 15 ST16C452/452PS ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition) ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). ISR BIT 4-7: (logic 0 or cleared is the default condition) Not Used - initialized to a logic 0. Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. BIT-2 Word length Stop bit length (Bit time(s)) 1 1-1/2 2 0 1 1 5,6,7,8 5 6,7,8 LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity. (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1's in the transmitted. The receiver must be programmed to check the same format. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced. (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. BIT-1 0 0 1 1 BIT-0 0 1 0 1 Word length 5 6 7 8 LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. Rev. 3.20 16 ST16C452/452PS LCR Bit-5 X 0 0 1 1 LCR Bit-4 X 0 1 0 1 LCR Bit-3 0 1 1 1 1 Parity selection loop-back mode this bit is use to write the state of the modem -RI interface signal. No parity Odd parity Even parity Force parity odd parity Forced even parity MCR BIT-3: (Used to control the modem -CD signal in the loop-back mode.) Logic 0 = Forces INT (A-B) outputs to the three state mode. (normal default condition) In the Loop-back mode, sets -CD internally to a logic 1. Logic 1 = Forces the INT (A-B) outputs to the active mode. In the Loop-back mode, sets -CD internally to a logic 0. MCR BIT-4: Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics). MCR BIT 5-7: Not Used - initialized to a logic 0. Line Status Register (LSR) This register provides the status of data transfers between. the 452/452PS and the CPU. LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition) Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled. (normal default condition) Logic 1 = Divisor latch and enhanced feature register enabled. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. LSR BIT-0: Logic 0 = No data in receive holding register. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register. LSR BIT-1: Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the RHR is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the RHR, therefore the data in the RHR is not corrupted by the error. LSR BIT-2: Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. MCR BIT-2: This bit is used in the Loop-back mode only. In the Rev. 3.20 17 ST16C452/452PS LSR BIT-3: Logic 0 = No framing error. (normal default condition) Logic 1 = Framing error. The receive character did not have a valid stop bit(s). LSR BIT-4: Logic 0 = No break condition. (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). LSR BIT-5: This bit indicates that the 452/452PS is ready to accept new characters for transmission. This bit causes the 452/452PS to issue an interrupt to the CPU when the transmit holding register is empty and the interrupt enable is set. Logic 0 = Transmit holding register is not empty. (normal default condition) Logic 1 = Transmit holding register is empty. When this bit is a logic 1, the CPU can load new character into the Transmit Holding Register for transmission. changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change. (normal default condition) Logic 1 = The -DSR input to the 452/452PS has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-2: Logic 0 = No -RI Change. (normal default condition) Logic 1 = The -RI input to the 452/452PS has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic 0 = No -CD Change. (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-4: Normally MSR bit-4 bit is the compliment of the -CTS input. However in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loop-back mode, this bit is equivalent to the DTR bit in the MCR register. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to MCR bit-2 in the MCR register. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loop-back mode this bit is equivalent to MCR bit-3 in the MCR register. Note: Whenever any MSR bit 0-3: is set to logic "1", a MODEM Status Interrupt will be generated. LSR BIT-6: Logic 0 = Transmitter holding and shift registers are full. Logic 1 = Transmitter holding and shift registers are empty (normal default condition). LSR BIT-7: Not Used - initialized to a logic 0. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the 452/452PS is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the 452/452PS has Rev. 3.20 18 ST16C452/452PS Scratchpad Register (SPR) The ST16C452/452PS provides a temporary data register to store 8 bits of user information. SR BIT-3: Logic 0 = -ERROR input is a logic 0. Logic 1 = -ERROR input is a logic 1. (normal inactive state) SR BIT-4: Logic 0 = SLCT input is a logic 0. (normal inactive state) Logic 1 = SLCT input is a logic 1. SR BIT-5: Logic 0 = PE input is a logic 0. (normal inactive state) Logic 1 = PE input is a logic 1. SR BIT-6: Logic 0 = -ACK input is a logic 0. Logic 1 = -ACK input is a logic 1. (normal inactive state) SR BIT-7: Logic 0 = BUSY input is a logic 0 Logic 1 = BUSY input is a logic 1 (normal inactive state) Command Register (COM) This register provides the printer port input logical states and the status of the printer interrupt INIT, which is based on the state of CON bit-1. PRINTER PORT REGISTER DESCRIPTIONS Port Register (PR) PR BIT 0-7: Printer Data port (Bi-directional) - These pins are the eight bit data bus for transferring information to or from an external device (usually a printer). D0 is the least significant bit. PD7-PD0 are latched during a write cycle (output mode). I/O Select Register (IOSEL) [452PS only] This register is used in conjunction with the state of BIDEN to set the direction (input/output) of the PD7PD0 data bus. This register is used only when BIDEN is a logic 0. Logic 55 (Hex) + BIDEN 0 = PD7-PD0 are set for output mode Logic AA (Hex) + BIDEN 0 = PD7-PD0 are set for input mode Status Register (SR) This register provides the printer port input logical states and the status of the interrupt -INTP based on the condition of the -ACK printer port interface signal. The logical state of these pins is dependent on external interface signals. SR BIT 1-0: Not Used - initialized to a logic 1. SR BIT-2: Logic 0 = an interrupt is pending When INTSEL is a logic 0, SR bit-2 basically tracks the -ACK input interface pin (returns to a logic 1 when the -ACK input returns to a logic 1). However when INTSEL is a logic 1, the latched mode is selected, SR bit-2 goes to a logic 0 with the -ACK input but does not return to a logic 1 until the end of the read cycle, i.e., reading SR will set this bit to a logic 1. Logic 1 = no interrupt is pending. (normal inactive state) COM BIT-0: -STROBE is a bi-directional signal with an open source driver and internal pull-up so that it may be wire-or'd with other outputs. COM bit-1 is used to read status while CON bit 1 is used to set an output state. If it is to function as an input, CON bit-1 shall be set to a logic 1 first. Logic 0 = -STROBE pin is a logic 1. (normal default condition) Logic 1 = -STROBE pin is a logic 0. COM BIT-1: -AutoFDXT is a bi-directional signal with an open source driver and internal pull-up so that it may be wire-or'd with other outputs. COM bit-1 is used to read status while CON bit 1 is used to set an output state. If it is to function as an input, CON bit-1 shall be set to Rev. 3.20 19 ST16C452/452PS a logic 1 first. Logic 0 = -AutoFDXT pin is a logic 1. (normal default condition) 1= -AutoFDXT pin is a logic 0. COM BIT-2: INIT is a bi-directional signal with an open source driver and internal pull-up so that it may be wire-or'd with other outputs. COM bit-2 is used to read status while CON bit 2 is used to set an output state. If it is to function as an input, CON bit-1 shall be set to a logic 1 first. Logic 0 = INIT pin is a logic 0. (normal default condition) Logic 1 = INIT pin is a logic 1. COM BIT-3: -SLCTIN is a bi-directional signal with an open source driver and internal pull-up so that it may be wire-or'd with other outputs. COM bit-1 is used to read status while CON bit 1 is used to set an output state. If it is to function as an input, CON bit-1 shall be set to a logic 1 first. Logic 0 = -SLCTIN pin is a logic 1 (normal default condition) Logic 1 = -SLCTIN pin is a logic 0 COM BIT-4: This bit allows the state of -INTP to be read back by the external CPU. Logic 0 = Interrupt (-INTP output) is disabled (normal default condition) Logic 1 = Interrupt (-INTP output) is enabled COM BIT 5-7: Not Used - initialized to a logic 1. Control Register (CON) This register provides control of the printer port output logical states and controls the printer interrupts INIT and -INTP. With the exception of PD 0-7 IN/OUT, the status of this register may be read by reading the COM register. CON BIT-0: The -STROBE output control bit is under software control, i.e., the hardware will not generate a strobe. It is up to software to return the state of -STROBE to the inactive (logic 1) state. The hardware driver is open drain so that -STROBE may be wire-or'd. The state of this bit can be read using COM bit-0. Logic 0 = -STROBE output is set to a logic 1. (normal default condition) Logic 1 = -STROBE output is set to a logic 0. CON BIT-1: The -AutoFDXT output control bit is set by software using CON bit-1. The hardware driver is open drain so that -AutoFDXT may be wire-or'd. The state of this bit can be read using COM bit-1. Logic 0 = -AutoFDXT output is set to a logic 1. (normal default condition) Logic 1 = -AutoFDXT output is set to a logic 0. CON BIT-2: The INIT output control bit is set by software using CON bit-2. The hardware driver is open drain so that INIT may be wire-or'd. The state of this bit can be read using COM bit-2. Logic 0 = INIT output is set to a logic 0. (normal default condition) Logic 1 = INIT output is set to a logic 1. CON BIT-3: The -SLCTIN output control bit is set by software using CON bit-3. The hardware driver is open drain so that -AutoFDXT may be wire-or'd. The state of this bit can be read using COM bit-3. Logic 0 = -SLCTIN output is set to a logic 1. (normal default condition) Logic 1 = -SLCTIN output is set to a logic 0. CON BIT-4: This bit enables or masks the printer interrupt output -INTP. The state of this bit can be read using COM bit4. Logic 0 = Disable -INTP output. (normal default condition) Logic 1 = Enable -INTP output. Rev. 3.20 20 ST16C452/452PS CON BIT-5: [452PS only] This bit is used in conjunction with the state of BIDEN to set the direction (input/output) of the PD7-PD0 data bus. Logic 0 + BIDEN 1 = PD7-PD0 are set for output mode (normal default condition) Logic 1 + BIDEN 1 = PD7-PD0 are set for input mode CON BIT 6-7: Not Used - initialized to a logic 1. SIGNALS TX A/B -RTS A/B -DTR A/B INT A/B, P PD0-PD7 -STROBE -AutoFDXT INIT -SLCTIN RESET STATE High High High Three state mode Low, output mode High, output mode High, output mode Low, output mode High, output mode ST16C452/452PS TION EXTERNAL RESET CONDI- REGISTERS (UART) IER ISR LCR MCR LSR MSR RESET STATE BITS 0-7=0 ISR BIT-0=1, ISR BITS 1-7=0 LCR BITS 0-7=0 MCR BITS 0-7=0 LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR BITS 0-3=0, MSR BITS 4-7=input signals REGISTERS Printer Port IOSEL SR COM CON RESET STATE IOSEL BITS-0-7=0 SR BITS 0-1=1, BITS 2-7=input signals COM BITS 0-4=0, BITS 5-7=1 CON BITS 0-5=0, BITS 6-7=1 Rev. 3.20 21 ST16C452/452PS AC ELECTRICAL CHARACTERISTICS TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max 17 8 5 10 35 0 40 35 25 10 40 0 40 20 5 50 40 40 1 45 45 24 45 75 15 30 10 10 40 1 75 10 25 5 5 40 1 10 25 0 30 15 5 40 35 35 1 40 40 24 40 0 10 25 0 30 25 15 Limits 5.0 Min Max 17 24 Units Conditions T1w,T2w T3w T6s T7d T7w T7h T9d T12d T12h T13d T13w T13h T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T39w T40s T41h T42d T43d TR N Clock pulse duration Oscillator/Clock frequency Address setup time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt -ACK pulse width PD7 - PD0 setup time PD7 - PD0 hold time Delay from -ACK low to interrupt low Delay from -IOR to reset interrupt Reset pulse width Baud rate devisor ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rclk ns ns Rclk ns ns ns ns ns ns ns Rclk 100 pF load 100 pF load 100 pF load 100 pF load 8 8 216-1 216-1 Rev. 3.20 22 ST16C452/452PS ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40 C to +85 C -65 C to 150 C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=2.97 - 5.5V unless otherwise specified. Symbol Parameter Limits 3.3 Min Max -0.3 2.4 -0.3 2.0 2.0 0.6 VCC 0.8 VCC 5.5 0.4 2.4 2.0 10 10 2.5 5 9 10 10 5 5 22 Limits 5.0 Min Max -0.5 3.0 -0.5 2.2 2.2 0.6 VCC 0.8 VCC 5.5 0.4 Units Conditions VILCK VIHCK VIL VIH VIH VOL VOL VOH VOH IIL ICL ICC CP RIN Clock input low level Clock and printer port input high level Input low level Input high level (Rev "E" and older) Input high level (Rev "F" and newer) Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Input capacitance Internal pull-up resistance V V V V V V V V V A A mA pF k IOL= 4 mA IOL= 4 mA IOH= -4 mA IOH= -1 mA Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors. Rev. 3.20 23 ST16C452/452PS A0-A 2 T 6s -C S V a lid A dd ress T7 h T 6s V a lid A dd ress T7 h T 7w A ct iv e T 7w T9 d A ct iv e -IO R A ct iv e T 12 d T 12 h V a lid D a ta T 12 d T 12 h D 0 -D 7 Va lid D a ta X 552 -R D -2 General read timing A 0-A2 T 6s -C S Va lid A d dr e s s T7 h T 6s Va lid A d dr e s s T7 h A ctive T1 3 w T1 5 d A ctive T1 3 w -I OW A ctive T 16s T1 6 h T 16s T1 6 h D 0-D 7 D a ta D a ta X 5 52 -R D -2 General write timing Rev. 3.20 24 ST16C452/452PS T2w T1w EXTERNAL CLOCK EX-CK-1 T3w External clock timing -IOW Active T17d -RTS -DTR Change of state Change of state -CD -CTS -DSR T18d INT Change of state Change of state T18d Active T19d Active Active Active Active Active -IOR T18d -RI Change of state X552-MD-1 Modem input/output timing Rev. 3.20 25 ST16C452/452PS START BIT DATA BITS (5-8) STOP BIT RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT NEXT DATA START BIT T20d Active T21d 5 DATA BITS 6 DATA BITS 7 DATA BITS INT -IOR Active 16 BAUD RATE CLOCK X552-RX-1 Receive timing Rev. 3.20 26 ST16C452/452PS START BIT DATA BITS (5-8) STOP BIT TX D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT NEXT DATA START BIT T22d Active Tx Ready 5 DATA BITS 6 DATA BITS 7 DATA BITS INT T23d -IOW Active T24d Active 16 BAUD RATE CLOCK X552-TX-1 Transmit timing Rev. 3.20 27 ST16C452/452PS T39w -ACK T40d INTP T43d -IOR T40s T42d NORMAL MODE INTERRUPT LATCHED MODE SELECT INTSEL T41h PD0-PD7 VALID DATA X552-PR-2 Printer port timing Rev. 3.20 28 ST16C452/452PS Rev. 3.20 29 ST16C452/452PS EXPLANATION OF DATA SHEET REVISIONS: FROM 3.10 TO 3.20 CHANGES DATE Added revision history. Added Device Status to front page. March 2004 Devices with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs except for XTAL1 and printer port inputs. Devices with top mark date code of of "EC YYWW" and older do not have 5V tolerant inputs. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet March 2004 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 3.20 30 |
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